A demand for high density and high integration of semiconductor devices in a semiconductor apparatus tends to heighten. In order to respond such a demand, miniaturization of a semiconductor device itself, and miniaturization of a device isolation region for isolating adjacent semiconductor devices tend to become increasingly important. Heretofore, as a method of forming a device isolation region, a LOCOS (Local Oxidation of Silicon) method in which an oxide film to become a device isolation region is formed has been generally utilized.
However, in the case where an oxide film having a minute pattern is formed using the LOCOS method, device isolation becomes incomplete because oxidation in a thickness direction does not proceed sufficiently. Further, in the case of forming an oxide film that has a sufficient thickness for isolating devices, the device isolation region spreads more than a predetermined region because oxidation in a lateral direction proceeds as well as the oxidation in the thickness direction. For this reason, the miniaturization of the device isolation region in the LOCOS method has its own limitation. Thus, an STI (Shallow Trench Isolation) method attracts attention as a device isolation technology in place of the LOCOS method (for example, see Japanese Laid-Open Patent Application No. 2001-237308).
In the STI method, a device isolation structure (trench isolation structure) is formed by forming trenches on a silicon substrate and filling a SiO2 film (insulating material) in each of the trenches. In this case, the SiO2 film is formed by protruding the surface of the SiO2 film so that the surface thereof is higher than the surface of the silicon substrate.
Heretofore, a trench isolation structure by the STI method is formed as follows. FIG. 8 is a drawing (vertical cross-sectional view) for explaining a conventional method of forming a semiconductor apparatus.
First, as shown in FIG. 8(a), apad oxide film 200 is formed on a silicon substrate 100 by subjecting the surface of the silicon substrate 100 to a thermal oxidation process.
Next, as shown in FIG. 8(b), a SiN film 300 is formed on the pad oxide film 200 by means of a CVD method. This SiN film 300 functions as a stopper when polishing the SiO2 film by means of a CMP (Chemical Mechanical Polishing) method at a post-process.
Next, as shown in FIG. 8(c), a resist layer 400 is formed on the SiN film 300 with a pattern corresponding to a region for forming devices (device forming region) by means of a photolithography method.
Next, as shown in FIG. 8(d), the SiN film 300 and the pad oxide film 200 are subjected to a dry etching process using the resist layer 400 as a mask, whereby the pad oxide film 200 and the SiN film 300 are patterned with a shape corresponding to the device forming region. The silicon substrate 100 is then subjected to an etching process using the patterned SiN film 300 as a mask, thereby forming trenches 500.
Next, as shown in FIG. 8(e), a SiO2 film 600 is formed on the silicon substrate 100 on which the pad oxide film 200, the SiN film 300 and the trenches 500 are formed by means of a plasma CVD method or the like so that the SiO2 film 600 is filled in each of the trenches 500.
Next, as shown in FIG. 8(f), the SiO2 film 600 is polished and flattened by means of the CMP method using the SiN film 300 as a stopper. Thus, the height of the surface of the SiO2 film 600 on the trench 500 becomes the height substantially corresponding with the height of the surface of the SiN film 300.
Next, as shown in FIG. 8(g), the SiN film 300 is eliminated by means of a wet etching process with a heated phosphoric acid.
Next, as shown in FIG. 8(h), the pad oxide film 200 is eliminated by means of a wet etching process with a fluoride acid.
Through the steps described above, the surface of the SiO2 film 600 in each of the trenches 500 becomes higher than the surface of the silicon substrate 100, thereby forming trench isolation structures (device isolation regions). The trench isolation structure makes a plurality of regions for forming devices to be separately formed on the surface of the silicon substrate 100.
Now, in the method described above, in order to flatten the SiO2 surface when flattening the SiO2 film 600 by means of the CMP method, the surface of the SiN film 300 is completely exposed, and the SiO2 film 600 is polished somewhat excessively. When the SiO2 film 600 is excessively polished, so-called dishing occurs at the step when the surface of the SiN film 300 is exposed and both the SiO2 film 600 and the SiN film 300 are polished at the same time. The dishing occurs because polishing does not proceed evenly between a narrow portion and a wide portion of the device isolation pattern due to a difference between the etching rates therefor.
Since the SiO2 film 600 is excessively polished at a relatively wide device isolation region in the dishing, isolation between the adjacent devices separated with such a wide device isolation region becomes incompletely, and/or a focus gap in the photolithography method occurs when forming gate electrodes on the SiO2 film 600 by patterning poly-silicon or the like, whereby failure of patterning formation occurs. As a result, there is a problem that characteristics of the semiconductor apparatus become impaired.
Further, in the method described above, the pad oxide film 200 is eliminated by means of a wet etching process using a hydrofluoric acid. In this regard, etching proceeds isotropically in the wet etching process using a hydrofluoric acid. For this reason, as shown in FIG. 8(h), an end portion of the SiO2 film 600 is subjected to etching, and as a result, concave portions of the SiO2 film 600 are generated at the boundaries between the SiO2 film 600 and the silicon substrate 100, whereby corner portions 501 are formed at the boundaries between the SiO2 film 600 and the silicon substrate 100.
In the case where, for example, a transistor is configured within each of the device forming regions of the silicon substrate 100 described above, a gate electrode is constructed to cover the corner portions 501. Thus, there is a problem that a leakage current occurs due to concentration of an electric field at the corner portions 501. In order to solve this problem, countermeasures such as round oxidation in which the corner portion 501 is shaped of round by means of a thermal oxidation process are taken (or adopted). However, since the number of manufacturing processes (or steps) for trench isolation structure is increased by providing such a process, manufacturing efficiency for the trench isolation structure tends to fall down.
Moreover, in the method described above, since the SiN film 300 is used as a stopper for the CMP method, the steps of forming and eliminating the SiN film 300 are required. This makes the number of manufacturing processes be increased.